Programmable and Adaptive Analog Filters using Arrays of Floating-Gate Circuits

In this paper we describe a programmable and adaptive jilter based on floating-gate technology. We review the basics offloating-gate techniques and how they enable programmable and adaptive jilter circuits. We describe our programmable filter concepts, and show experimental results of programmable Jilter operation. We also describe programming methods, and extend the programmability to a wide range of functions and circuits using the same approach. Further; we describe our techniques and custom programmer board for joating-gate programming of an IC. We show how to extend our programmable jilters as adaptive jilters both through weight perturbation methods and continuously adapting correlation rule methods. 1: Analog Computing Arrays We introduce the use of high density analog computing arrays for signal processing based on nonvolatile semiconductor memory cells. We base this model on an efficient computing paradigm in which highly parallel signal processing computations are performed through analog memory elements based on modified EEPROM cells. The high density analog computing arrays (referred to as computing arrays) require a core memory cells similar to a standard EEPROM or S R 4 M cell with a small amount of additional circuitry. The enabling technology of this approach is a lloatinggate circuit technology that allows for simultaneous storage, computation, and programming in each cell. Unlike digital memory, each cell acts as a multiplier that multiplies the analog input signal to that cell by an analog value stored in a floating gate. By performing the computation in the memory cells themselves we avoid the through-put bottlenecks found in most signal processing systems. We can also extend this computational approach to many other signal processing operations and algorithms in a straightforward manner. The range of applications for computable memories reaches from auditory and speech processing, to beam-forming, multidimensional signal processing, and radar computations, communications processing, and image processing and recognition. We believe that the high density analog computing arrays will be an important option for designers who want to implement advanced signal processing algorithms for embedded and very low-power systems. Our analog computing arrays are based on arrays of dense floating-gate transistors that provide non-volatile storage, compute a product between this stored weight and the inputs, allow for programming that does not affect the computation, and adapt due to correlations of input signals. Figure l a shows a general block-diagram of our floating-gate computing array. Each processor is composed of two floating-gate transistors, and therefore corresponds closely to EEPROM densities. The memory cells may be accessed individually (for readout or programming) or they may be used for full parallel computation within the array (as in matrix-vector multiplication or adaptation). Therefore, we have full parallel computation with the same circuit complexity and power 148 1522-869W01 $10.00(9 2001 IEEE